Ternara Semiconductor

Minus one, zero, plus one.Every step of proof, including the empty one.

Ternara Semiconductor designs ternary-weight compute blocks from written specifications and generators. Each block shows which steps of a five-step proof ladder it has reached: spec, simulation, FPGA, layout, silicon. The last step, silicon, is still empty, and we keep it on the page.

Binary logic, ternary weights. A trit is stored in two bits of binary CMOS.

As of 2026-10-10: no die has been returned from fabrication. No Ternara silicon has been measured.

Run the 200 reference vectors See the proof ladder

Yours? the first die with Ternara blocks can be yours As of 2026-10-10 no die has been returned from fabrication, so that place is still open. Next Tiny Tapeout windows close 2026-11-30 and 2026-12-07 (estimate by TT). Write to dmitrii@ternara.net.

538 models checked in the public Ternary Check scan Scan of 2026-10-10, 312 Hugging Face repositories. Headers are read; no weights are downloaded and no model is run. Software, not hardware.

2275 / 2275 replayed verdicts that agree with five reference reader builds Zero disagreements in the same scan. Readers: llama.cpp (two pins), the PrismML fork, bitnet.cpp, mortar.cpp.

89 / 109 catalogued numeric formats with bit-exact test vectors The other 20 are not bit-exact yet, and the catalogue says so.

Proof ladder

Five steps. The last one is empty.

A block climbs one step at a time. A step counts when there is a public run anyone can open, or a log whose sha256 is shown; such logs are available on request. A block may stop at any step, and the card says where it stopped.

Spec (reached by a block on this page)

A written specification fixes the arithmetic: a formal spec where one exists, otherwise the documented trit library of the spec compiler. Where RTL is generated, it is generated from that specification, not the other way round.

Simulation (reached by a block on this page)

The RTL runs in a simulator or a formal tool and is compared with an independent reference.

FPGA (Artix-7) (not reached)

A design runs on a third-party Artix-7 board, and a host checks its answers. A board is not a chip.

GDS + precheck (reached by a block on this page)

A layout is built in the open toolchain and accepted by the Tiny Tapeout precheck. This is not a submission and not timing sign-off.

Silicon (not reached)

A die comes back from fabrication and is measured. No Ternara block is on this step.

No block on this page is shown at the FPGA step. The one layout on this page is Corona, a format-checking tile, not a compute block.

This step is empty on purpose. As of 2026-10-10: no die has been returned from fabrication. No Ternara silicon has been measured.

Reference blocks

A family of reference blocks

Each card is one artifact that exists today, with its proof step, what it shows, what it does not show, and where the evidence lives. A step without a log is not claimed.

Concept render, not a fabricated device

BLOCK Asimulated

Ternary dot-product lane

27 weights against 27 activations, with no multiplier.

A combinational block that takes 27 weights and 27 activations, each a trit from {−1, 0, +1} coded in two bits, and returns their dot product. Each pair adds, subtracts or is skipped. The module is trit27_dot_product, generated by the spec compiler from its trit library.

Proof step

Not shown: no FPGA run, no layout, no die; activations are trits, not the 8-bit activations of BitNet-class models.

What it shows · What it does not show

What it shows

200 vectors (184 drawn from a recorded seed and 16 edge cases) give the same result on three independent paths: a Python reference, a separate JavaScript reference and RTL simulation in Icarus Verilog.
A reference with one trit flipped on purpose makes the same check fail, so the check can catch an error.

What it does not show

No FPGA run of this module is claimed here.
No layout and no die.
Simulation shows logic, not speed or energy.
Both inputs are trits; BitNet-class models use 8-bit activations, which this lane does not take.

Where it fits

The add, subtract or skip pattern of a ternary-weight layer. This lane takes ternary activations too; BitNet-class models use 8-bit activations, so a real layer needs a ternary × int8 lane, which is not built. Attention, embeddings and the KV cache are not ternary and need other blocks.

Evidence

Cross-check log: Python = JavaScript (evidence/ref.mjs) = RTL; available on request

sha256 a3c9536a0ad7eff35ffe3c36c4c304ebfd07fcfa3094d20eeb74a1312776a8da

Reference vectors used by the test bench (published with this page: data/vectors.json)

Separate JavaScript reference used in the cross-check; available on request

sha256 6483a06f129d36e8e4d5dd5f8213a9485be17251a07e726b572fbd2eac478b2a

Generated trit library (RTL source); available on request

sha256 149ce09c8a4c995b335a632ae5ad32a5421aab4aab708ca98461d56b4647a28e

Not measured: power, signed-off timing

Concept render, not a fabricated device

BLOCK Bsimulated

Formally checked micro-classifier

A toy network whose generated RTL is proved equal to its reference.

A tiny classifier with 8 binary inputs, 3 classes and 24 ternary weights, written as a formal spec. The spec compiler generates its RTL, and a SAT-based proof in Yosys checks that this RTL equals a reference model on every possible input.

Proof step

Not shown: a toy with 24 weights, not a useful model; no FPGA run, no layout, no die.

What it shows · What it does not show

What it shows

The RTL generated from the spec equals the reference on all inputs: a formal proof, not a sample of tests.
A mutation run breaks the reference on purpose, and the proof then fails, so the proof is not empty.

What it does not show

It is a toy, not a useful model.
No FPGA run of this block is claimed here.
No layout and no die.

Where it fits

A demonstrator of the method: spec, generated RTL and proof travel together. It shows how a larger ternary block could be checked; it is not a production workload.

Evidence

Formal proof log (prove run); available on request

sha256 8db7c1f769a239a9ae724a1458078e68b0fd6ab3f3a1cfad3b5e701bf645614d

Mutation run log (prove run with --mutate); available on request

sha256 9b449421ff7bbe871944cb36174986f77f6903cc211ff8d45533a6d8f191eb55

Not measured: power, signed-off timing

Concept render, not a fabricated device

BLOCK CGDS + precheck, not submitted

Format-oracle tile (Corona)

A small layout that describes number formats and decodes them. Not a ternary compute block.

Corona is a Tiny Tapeout tile design (4x4 tiles) for the GF180MCU open process kit. It holds a fixed table of numeric-format descriptions and reference decoders whose outputs are FP32 or INT32 values. Its job is to answer one question correctly: how are these bits meant to be read?

Proof step

Not shown: not submitted, not timing sign-off, no die; it checks number formats and does not compute ternary dot products.

What it shows · What it does not show

What it shows

In a public CI run, the layout passes the open-toolchain flow (LVS and antenna checks) and the Tiny Tapeout precheck, whose KLayout DRC deck reports zero items.
Gate-level simulation passes in the same run.
An executable acceptance policy (Phase A, a sealed formal spec) rejects planted mutants and altered vectors.

What it does not show

Not submitted to any shuttle.
Not timing sign-off: the slow corner shows setup violations.
The flow also warns about max slew and max capacitance.
No die and no measurement.
It does not compute ternary dot products.

Where it fits

Format checking. A ternary-weight accelerator must read weight-packing formats exactly as the software does. This tile is a hardware reference for that check, next to the Ternary Check software.

Evidence

CI run log: GDS, precheck, gate-level tests (2026-10-04); available on request

Not measured: power, signed-off timing

Test bench

A 27-trit dot product you can check

Set 27 weights and 27 activations, each −1, 0 or +1. Each pair adds, subtracts or is skipped, so the sum needs no multiplier. In hardware each trit is stored as a two-bit code: 00 is −1, 01 is 0, 10 is +1, and 11 is reserved.

weights (trits)

activations (trits)

0dot product

software model (JavaScript), not a chip output

The 200 vectors are 184 drawn from a recorded seed and 16 edge cases. They went through three independent paths: a Python reference, a separate JavaScript reference (evidence/ref.mjs) and the RTL module trit27_dot_product simulated in Icarus Verilog. All three agree. A reference with one trit flipped on purpose makes the check fail, so the check can catch an error. This page recomputes the stored vectors with its own JavaScript and compares them with the stored results; that page code was not part of the three-way check. Evidence: the cross-check log (its sha256 is on card A; the log is available on request) and data/vectors.json, which this page loads. This shows logic in simulation, not a measurement of hardware.

Weight bytes

What three states save in memory

Store the same weights in different formats and count the bytes. Two bits hold a trit with one code to spare. Five trits fit in one byte, because 3^5 = 243 is below 256. Not every weight in a model is ternary: in Microsoft's BitNet b1.58 2B4T the embedding table stays in bf16, and attention and the KV cache stay wider.

number of weights2.0B

BF1616 bit/weight4.0 GB

INT88 bit/weight2.0 GB

INT4 (no scale)4 bit/weight998 MB

TQ2_0 (llama.cpp: 2 bits per trit, with scale)2.0625 bit/weight514 MB

TQ1_0 (llama.cpp: 5 trits per byte, with scale)1.6875 bit/weight421 MB

log2(3): the information floor for a trit1.585 bit/weight395 MB

Memory arithmetic, not a measurement. It says nothing about speed, energy or accuracy. No accuracy comparison between these formats has been made here.

Prior art

Others already work here

Ternary weights are not new, and neither is ternary hardware. Academic groups, Tiny Tapeout designers and software runtimes work with ternary weights, and some stand on higher steps of the ladder than we do. Each row says who reports it, with a link we opened on 2026-10-10. The level is our reading of the source.

No comparison is possible: we have no silicon measurements.

WhoWhat they reportLevel (our reading of the source)Date

TeLLMe (v1, v2) Ye Qiao, Zhiheng Chen, Yifan Zhang, Yian Wang, Sitao Huang

FPGA accelerator for prefill and decode of ternary-weight language models on an edge board.

The authors report end-to-end prefill and decode on an AMD KV260 board within a 7 W power budget (arXiv abstract); a v2 paper (arXiv 2510.15926) reports a table-lookup matmul variant within 5 W. · Source FPGA2025-04

TerEffic Chenyang Yin, Zhenyu Bai, Pranav Venkatram, Shivam Aggarwal, Zhaoying Li, Tulika Mitra

FPGA inference of ternary-weight language models: a small model held fully on-chip and a larger one using HBM.

The authors report (paper v2) a 370M-parameter model running fully on-chip and a 2.7B-parameter variant with HBM on a single FPGA board; their comparisons with Jetson Orin Nano and A100 are their own and not independently checked. · Source FPGA2025-02

TENET Zhirui Huang, Rui Ma, Shijie Cao, Ran Shu, Ian Wang, Ting Cao, Chixiao Chen, Yongqiang Xiong

LUT-centric architecture for ternary-weight language model inference: an FPGA prototype plus an ASIC estimate.

The authors report an FPGA prototype on Intel Stratix 10 MX and an ASIC estimate from Synopsys Design Compiler synthesis in a 28 nm process; the paper is also listed on a Microsoft Research page. · Source FPGA2025-09

VitaLLM Zi-Wei Lin, Tian-Sheuan Chang

Compact accelerator design for ternary-weight language models with dependency-aware scheduling.

The authors report a standard-cell design in TSMC 16 nm, with figures from an analytical model checked against post-layout gate-level simulation. A companion paper (arXiv 2605.00320) reports a "16 nm silicon prototype"; its abstract does not state how it was measured. · Source silicon (companion paper; measurement method not stated)2026-04

BitROM Wenlun Zhang, Xinyu Li, Shimpei Ando, Kentaro Yoshioka

Compute-in-ROM architecture for 1.58-bit language model weights.

The authors report a 65 nm CMOS compute-in-ROM design for 1.58-bit weights (ASP-DAC 2026); the Ankhdjet paper describes it as evaluated in layout and simulation. · Source simulation2025-09

Slim-Llama Sangyeob Kim, Jungwan Lee, Byeongju Kim, Hoi-Jun Yoo (Yonsei University, KAIST)

Low-power language model processor with binary and ternary weights (ISSCC 2025).

The authors' Hot Chips 2025 poster shows a chip photograph and gives benchmark conditions of 50 MHz at 0.65 V and 200 MHz at 1.0 V; the VitaLLM comparison table lists it as a 28 nm ASIC with power measured at 200 MHz. · Source silicon2025

Tiny ASIC 1.58-bit matrix multiplication rejunity

Open Verilog design of a 1.58-bit matrix-multiplication array for the Tiny Tapeout shuttle.

The repository describes a design that packs 5 trits per byte for Tiny Tapeout. Tiny Tapeout lists it on TT06 as project 142, "Ternary 1.58-bit x 8-bit matrix multiplier" (ReJ aka Renaldas Zioma), and lists TT06 as shipped on 2024-12-07 (read 2026-10-10). No chip measurements are published. · Source silicon (TT06, shipped per TT; no measurements published)2024

T3 (Tiny Ternary Tapeout) Arnav Sacheti, Jack Adiletta

Ternary matmul processor on the TT09 Tiny Tapeout shuttle: weights in {-1, 0, +1} handled by add, subtract or skip.

The Tiny Tapeout page describes the design and how to connect it. Tiny Tapeout lists TT09 chips as TBD (read 2026-10-10); the Ankhdjet paper's table lists it as manufactured. · Source simulation (TT09 chips listed as TBD by TT)2024

Ankhdjet Mohnish Pai

Open-source compiler for mask-programmed ternary compute-in-ROM on an open PDK (SKY130).

The author reports DRC and LVS clean results and clean timing in an open toolchain, energy per weight read from extracted-parasitic simulation, and a design on the ttsky26c Tiny Tapeout shuttle with chips expected in 2027. · Source submitted (ttsky26c), not yet returned2026-08

TERNARO SHAOS (hackaday.io)

Concept of an FPGA-like integrated circuit built on balanced ternary logic.

The project page describes a 7x9 grid of configurable ternary blocks; the last log entry is from 2018, and a 2023 comment by the author mentions experiments with Tiny Tapeout. · Source concept (project notes)2018-07

Ternary logic on carbon-nanotube source-gating transistors Xuehao Zhu, Lian-mao Peng, Yu Cao, Qiliang Li, Xuelei Liang, Panpan Zhang and co-authors (Peking University, BUPT)

Ternary inverters, gates and a ternary SRAM cell built from carbon-nanotube transistors; a small ternary neural network evaluated in simulation.

The authors report measured ternary inverters, NMIN/NMAX gates and a 6T ternary SRAM cell, and a simulated 8x8-neuron ternary network for digit classification (Science Advances, 2025, DOI 10.1126/sciadv.adt1909). · Source devices measured (carbon nanotubes, not silicon CMOS)2025-01

Huawei ternary logic gate patent application CN119652311A Huawei (inventors Hu Hailin, Huang Mingqiang, Zhao Guangchao, Li Wenshuo, Wang Yunhe)

Patent application for a ternary logic gate circuit, computing circuit, chip and electronic device.

Google Patents lists the application as filed 2023-09-18, published 2025-03-18, status pending (Google Patents notes that status is not a legal conclusion). · Source patent application2025-03

ART-9 Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee (POSTECH)

9-trit RISC processor core for ternary logic, evaluated by emulation on a binary FPGA and with CNTFET device models.

The authors report Dhrystone results from FPGA-level ternary-logic emulation on Intel Stratix-V and from 32 nm CNTFET models (DATE 2022). · Source FPGA2022

5500FP Claudio Lorenzo La Rosa (independent researcher)

24-trit balanced ternary RISC processor implemented on an FPGA.

Hackaday reports the FPGA implementation; in the comments a reader argues that each trit is emulated with two bits, and the author rejects the word "emulation". The maker's site (ternary-computing.com) takes preorders; its hardware claims are the maker's own. · Source FPGA2026-03

Setun Sergei Sobolev and Nikolay Brusentsov, Moscow State University

Balanced ternary computer built in series in the USSR.

Wikipedia reports that 50 Setun machines were built under the leadership of Sergei Sobolev and Nikolay Brusentsov, with serial production from 1959 to 1965. · Source product1959

BitNet b1.58 and bitnet.cpp Microsoft

Ternary-weight model family and open inference framework for CPU and GPU.

Microsoft's README lists CPU and GPU kernels under the MIT license and says NPU support is coming next, without a date. The 2024 paper 'The Era of 1-bit LLMs' says this work opens the door to hardware built specifically for 1-bit models. · Source product2026-07

Ternary Bonsai PrismML

Open-weight ternary language models running on existing hardware.

PrismML reports 8B, 4B and 1.7B models with weights in {-1, 0, +1} and group-wise FP16 scales under Apache 2.0, run through MLX on Apple devices; the speed figures on the page are PrismML's own. · Source product2026-04

BitNet on Qualcomm Hexagon ENERZAi (republished by the Edge AI and Vision Alliance)

Custom kernels running a ternary-weight model on an existing mobile NPU.

ENERZAi reports running BitNet b1.58 2B on the Hexagon NPU of a Qualcomm QCS6490 and states that QNN has no support for ternary, 1.58-bit operations. · Source product2026-06

Taalas HC1 Taalas (Toronto)

Technology demonstrator chip with one language model hard-wired into the design.

heise reports that Taalas announced HC1 with Llama 3.1 8B hard-wired on TSMC N6. AMD announced a definitive agreement to acquire Taalas on 2026-08-06, subject to closing conditions and regulatory approvals. · Source silicon2026-02

Path to a die

What a die would take

Tiny Tapeout pools small open designs on shared shuttles. The dates below are published by Tiny Tapeout and can move. Nothing here is a delivery promise.

Specs and simulation

Reference blocks are written as specs and checked in simulation against independent references. Each block card shows its own status and evidence.

Layout experience: a format-checking tile (Corona)

Corona has GDS + precheck, not submitted: a GF180MCU layout built in the open toolchain, with a public CI run. It checks number formats and is not a ternary compute block, so this is layout experience, not a compute block on its way to a die.

Decide on a small honest block

Candidate: one 1x1 to 1x2 tile, one trit encoding, a real gate-level test and the 200 reference vectors. Whether to submit is not decided (default: do not submit).

Shuttle window

If the founders decide to submit: TTSKY26d closes 2026-11-30, TTGF26c closes 2026-12-07 (estimate by TT). Tiles can sell out before submissions close.

Die delivery and bring-up

For these shuttles TT expects chips on 2027-05-12 and shipping on 2027-06-09 (estimate by TT). Bring-up and measurement can start after delivery; no result is promised before that.

Silicon measurement

Earlier designs appear in the public Tiny Tapeout indexes for TTSKY26a/b; their status has not yet been confirmed by Tiny Tapeout. As of 2026-10-10: no die has been returned from fabrication. No Ternara silicon has been measured. The Silicon step of the ladder stays empty until a die is measured and its log is published.

TTSKY26d

process: SkyWater SKY130 (ChipFoundry batch CI-2612)
submissions close: 2026-11-30
return (TT est.): 2027-05-12
shipping (TT est.): 2027-06-09

Tiny Tapeout calculator, read 2026-10-10 (Academic/Industry mode): 70 EUR per tile, 300 EUR per devkit, 15 EUR shipping per devkit. Dates and amounts are estimates by TT, not an offer. The devkit carries one shared multi-project die on a removable breakout board.

TTGF26c

process: GlobalFoundries GF180MCU (wafer.space Run 3)
submissions close: 2026-12-07
return (TT est.): 2027-05-12
shipping (TT est.): 2027-06-09

Tiny Tapeout calculator, read 2026-10-10 (Academic/Industry mode): 70 EUR per tile, 300 EUR per devkit, 15 EUR shipping per devkit; this shuttle is run by wafer.space. Per TT's demo-board page, on GF180 devkits the die is bonded to the board and cannot be removed. Dates and amounts are estimates by TT, not an offer.

estimate by TT · tinytapeout.com (opens in a new tab)

Contact

Talk to Ternara

Dmitrii Fedorov Co-founder, Ternara. Business, partnerships and capital. dmitrii@ternara.net

Every claim on this page has an id in our claims ledger and a source. If one is wrong, write to us and we will correct it with a dated note.